Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID

dc.contributor.authorBENFICA, J.
dc.contributor.authorGREEN, B.
dc.contributor.authorPORCHER, B. C.
dc.contributor.authorPOEHLS, L. B.
dc.contributor.authorVARGAS, F.
dc.contributor.authorMEDINA, N. H.
dc.contributor.authorADDED, N.
dc.contributor.authorAGUIAR, V. A. P. DE
dc.contributor.authorMACCHIONE, E. L. A.
dc.contributor.authorAGUIRRE, F.
dc.contributor.authorMarcilei Aparecida Guazzelli
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-7110-7241
dc.date.accessioned2022-01-12T21:58:55Z
dc.date.available2022-01-12T21:58:55Z
dc.date.issued2016-05-17
dc.description.abstract© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.
dc.description.firstpage887
dc.description.lastpage889
dc.identifier.citationBENFICA, J.; GREEN, B.; PORCHER, B. C.; POEHLS, L. B.; VARGAS, F.; MEDINA, N. H.; ADDED, N.;AGUIAR, V. A. P. DE; MACCHIONE, E. L. A.; AGUIRRE, F.; GUAZZELLI, M. A. Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID. 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2016, p. 887-889, mayo, 2016.
dc.identifier.doi10.1109/APEMC.2016.7522900
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3894
dc.relation.ispartof2016 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2016
dc.rightsAcesso Restrito
dc.subject.otherlanguageCombined Test
dc.subject.otherlanguageEMI
dc.subject.otherlanguagePower-Supply Noise
dc.subject.otherlanguageSEU Sensitivity
dc.subject.otherlanguageSpartan 3E
dc.subject.otherlanguageSRAM-Based FPGA
dc.subject.otherlanguageTID
dc.titleAnalysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID
dc.typeArtigo de evento
fei.scopus.citations6
fei.scopus.eid2-s2.0-84983681767
fei.scopus.subjectCombined test
fei.scopus.subjectPower-supply noise
fei.scopus.subjectSEU Sensitivity
fei.scopus.subjectSpartan-3
fei.scopus.subjectSRAM-based FPGA
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84983681767&origin=inward
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