Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs

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dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorMARTINO, J. A.
dc.contributor.authorRASKIN, J. P.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T22:05:32Z
dc.date.available2022-01-12T22:05:32Z
dc.date.issued2006-04-26
dc.description.abstractIn this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and Gate-All-Around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion. © 2006 IEEE.
dc.description.firstpage187
dc.description.lastpage194
dc.identifier.citationPAVANELLO, M. A.; CERDEIRA, A.; MARTINO, J. A.; RASKIN, J. P.; FLANDRE, D. Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs. Proceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 - Final Program and Technical Digest, p. 187-194, 2006
dc.identifier.doi10.1109/ICCDCS.2006.250859
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4345
dc.relation.ispartofProceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 - Final Program and Technical Digest
dc.rightsAcesso Restrito
dc.subject.otherlanguageDouble gate
dc.subject.otherlanguageHarmonic distortion
dc.subject.otherlanguageLinearity
dc.subject.otherlanguageMOSFET
dc.titleImpact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs
dc.typeArtigo de evento
fei.scopus.citations7
fei.scopus.eid2-s2.0-34250757086
fei.scopus.subjectDouble gate
fei.scopus.subjectGate All Around architecture
fei.scopus.subjectGraded channels (GC)
fei.scopus.subjectSinusoidal signals
fei.scopus.updated2024-08-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=34250757086&origin=inward
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