Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors
N/D
Tipo de produção
Artigo de evento
Data de publicação
2012-03-17
Texto completo (DOI)
Periódico
2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
Editor
Texto completo na Scopus
Citações na Scopus
9
Autores
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
Orientadores
Resumo
This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode. © 2012 IEEE.
Citação
DE SOUZA, M.; PAVANELLO, M. A. ; FLANDRE, D. Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March, 2012.
Palavras-chave
Keywords
Analog Parameters; MOSFET; Self-Cascode Transistor; Silicon-On-Insulator
Assuntos Scopus
Analog parameters; Analog performance; Fully depleted; Fully depleted SOI; MOS-FET; Output conductance; P-type; Silicon on insulator; Single transistors; SOI transistors; Voltage gain