Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range
N/D
Tipo de produção
Artigo
Data de publicação
2019
Texto completo (DOI)
Periódico
Solid-State Electronics
Editor
Texto completo na Scopus
Citações na Scopus
9
Autores
Pavanello M.A.
Cerdeira A.
Doria R.T.
Ribeiro T.A.
Avila-Herrera F.
Estrada M.
Orientadores
Resumo
© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
Citação
Pavanello, Marcelo A.; CERDEIRA, Antonio; Doria, Rodrigo Trevisoli; RIBEIRO, Thales Augusto; HERRERA, FERNANDO AVILA; ESTRADA, MAGALI. Compact Modeling of Triple Gate Junctionless Mosfets for Accurate Circuit Design in a Wide Temperature Range. SOLID-STATE ELECTRONICS, v. 159, p. 116-122, 2019.
Palavras-chave
Keywords
Compact model; Junctionless nanowire transistor; Temperature
Assuntos Scopus
Circuit designs; Compact model; Electrical characteristic; Model validation; Nanowire transistors; Physically based; Triple-gate; Wide temperature ranges