Operation of double gate graded-channel transistors at low temperatures
dc.contributor.advisorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.author | MARTINO, J. A. | |
dc.contributor.author | CHUNG, T. M. | |
dc.contributor.author | KRANTI, A. | |
dc.contributor.author | RASKIN, J. P. | |
dc.contributor.author | FLANDRE, D. | |
dc.date.accessioned | 2023-08-26T23:50:59Z | |
dc.date.available | 2023-08-26T23:50:59Z | |
dc.date.issued | 2003-10-16 | |
dc.description.abstract | This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio. | |
dc.description.firstpage | 50 | |
dc.description.lastpage | 60 | |
dc.description.volume | 27 | |
dc.identifier.citation | PAVANELLO, M. A.; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D. Operation of double gate graded-channel transistors at low temperatures. Proceedings - Electrochemical Society, v. 27, p. 50-60, oct. 2003. | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/5070 | |
dc.relation.ispartof | Proceedings - Electrochemical Society | |
dc.rights | Acesso Restrito | |
dc.title | Operation of double gate graded-channel transistors at low temperatures | |
dc.type | Artigo de evento | |
fei.scopus.citations | 1 | |
fei.scopus.eid | 2-s2.0-21644477030 | |
fei.scopus.subject | Channel regions | |
fei.scopus.subject | Double gate (DG) | |
fei.scopus.subject | Drain currents | |
fei.scopus.subject | Graded-channels | |
fei.scopus.updated | 2024-11-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=21644477030&origin=inward |