The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs

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dc.contributor.authorGALEMBECK, E.H. S.
dc.contributor.authorSILVA, G. A. D.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-04-01T06:03:08Z
dc.date.available2022-04-01T06:03:08Z
dc.date.issued2021-08-27
dc.description.abstract©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.
dc.identifier.citationGALEMBECK, E.H. S.; SILVA, G. A. D.; GIMENEZ, S. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices, Aug. 2021.
dc.identifier.doi10.1109/SBMicro50945.2021.9585737
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4462
dc.relation.ispartofSBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguage3-d numerical simulations
dc.subject.otherlanguageHalf-diamond mosfet
dc.subject.otherlanguageLce
dc.subject.otherlanguageNon-standard gate geometries
dc.subject.otherlanguagePamdle
dc.titleThe Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-85126118672
fei.scopus.subject3-D numerical simulation
fei.scopus.subjectElectrical behaviors
fei.scopus.subjectGate geometry
fei.scopus.subjectHalf-diamond mosfet
fei.scopus.subjectLce
fei.scopus.subjectMOS-FET
fei.scopus.subjectMOSFETs
fei.scopus.subjectNon-standard gate geometry
fei.scopus.subjectPamdle
fei.scopus.subjectSecond generation
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85126118672&origin=inward
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