Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors
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7
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2012-10-04
Autores
Rodrido Doria
TREVISOLI, R. D.
Michelly De Souza
FERAIN, I.
DAS, S.
Marcelo Antonio Pavanello
TREVISOLI, R. D.
Michelly De Souza
FERAIN, I.
DAS, S.
Marcelo Antonio Pavanello
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https://orcid.org/0000-0003-4448-4337
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Proceedings - IEEE International SOI Conference
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DORIA, R.; TREVISOLI, R. D.; DE SOUZA, M.; FERAIN, I.; DAS, S.; PAVANELLO, M. A. Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors. Proceedings - IEEE International SOI Conference. Oct. 2012.
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Multi-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an improved coupling between gates and channel, conventional inversion mode (IM) multi-gate structures such as Trigate and FinFETs present p-n junctions between source/drain and channel, which can become an important bottleneck for ultimate technologies in which the formation of ultra-sharp junctions is needed in order to avoid the source/drain dopants diffusion into the channel. A novel multi-gate architecture so-called Junctionless Nanowire Transistor (JNT) was recently developed to overcome this bottleneck [2-3]. The JNT consists of a silicon nanowire surrounded by gate stack and is different from multi-gate IM devices due to its doping profile which is heavy and constant between source, channel and drain without any dopant gradients. The longitudinal sections of both a pMOS and an nMOS JNT are shown in Fig. 1 where the p-type is doped with boron and the n-type ones with phosphorous. The silicon nanowire needs to have a square-section small enough to be fully depleted at low gate voltages, turning off the device. Above threshold, the current flows mainly due to bulk conduction [4]. Several papers have shown the potentiality of the JNT for technological nodes beyond 10 nm [2-6] since it provides better DIBL, subthreshold slope and analog properties than IM multi-gate transistors of similar dimensions [5,6]. Although the Low-Frequency Noise (LFN) of JNTs has been treated in different papers [7,8], only long devices have been evaluated up to now and in none of them the LFN of pMOS was addressed as proposed in the current paper. © 2012 IEEE.