Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
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2006-09-01
Autores
SANTOS, C. D. G. DOS
Marcelo Antonio Pavanello
Joao Antonio Martino
Marcelo Antonio Pavanello
Joao Antonio Martino
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Periódico
ECS Transactions
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SANTOS, C. D. G. DOS; PAVANELLO, M. A.; MARTINO, J. A. Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C. ECS Transactions, v. 4, n. 1, p. 283-291, sept. 2006.
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This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.