Compact model for short-channel symmetric double-gate junctionless transistors

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dc.contributor.authorAvila-Herrera F.
dc.contributor.authorCerdeira A.
dc.contributor.authorPaz B.C.
dc.contributor.authorEstrada M.
dc.contributor.authorIniguez B.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:11Z
dc.date.available2019-08-19T23:45:11Z
dc.date.issued2015
dc.description.abstract© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 10<sup>18</sup> and 1 × 10<sup>19</sup> cm<sup>-3</sup>, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.
dc.description.firstpage196
dc.description.lastpage203
dc.description.volume111
dc.identifier.citationAVILA, FERNANDO; CERDEIRA, Antonio; PAZ, Bruna Cardoso; CUETO, Magali Estrada; INIGUEZ, Benjamin; Pavanello, Marcelo Antonio. Compact model for short-channel symmetric double-gate junctionless transistors. Solid-State Electronics, v. 111, p. 196-203, 2015.
dc.identifier.doi10.1016/j.sse.2015.06.009
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1108
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageCompact analytical model
dc.subject.otherlanguageDouble-gate JLT
dc.subject.otherlanguageJLT
dc.subject.otherlanguageSCE model
dc.titleCompact model for short-channel symmetric double-gate junctionless transistors
dc.typeArtigo
fei.scopus.citations19
fei.scopus.eid2-s2.0-84934991637
fei.scopus.subjectDoping concentration
fei.scopus.subjectDouble gate
fei.scopus.subjectJLT
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectShort-channel effect
fei.scopus.subjectSymmetric double gate
fei.scopus.subjectThreshold voltage roll-off
fei.scopus.subjectThreshold voltage shifts
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84934991637&origin=inward
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