Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation

dc.contributor.authorGALEMBECK, E. H. S.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorRENAUX, C.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-01-12T21:56:43Z
dc.date.available2022-01-12T21:56:43Z
dc.date.issued2019-01-05
dc.description.abstract© 2019, Brazilian Microelectronics Society. All rights reserved.The present paper performs an experimental comparative study of the main switching electrical parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named Octo SOI MOSFET (OSM), in comparison with the typical rectangular one, regarding a large range of temperature, varying from 300 K to 573 K. The devices were manufactured in a 2 µm fully-depleted SOI (CMOS) technology and are n-type. The results have shown that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE), which are intrinsic effects of the gate octagonal structure of the MOSFET. Besides, it is able to present a higher electrical performance as compared to its rectangular SOI MOSFET (RSM) counterpart (same channel width and bias conditions). As an illustration, the OSM on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller as compared to those found in its RSM counterpart.
dc.description.firstpage1
dc.description.issuenumber2
dc.description.lastpage8
dc.description.volume14
dc.identifier.citationGALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; GIMENEZ, S. Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation. Journal of Integrated Circuits and Systems,v. 14, n. 1, p. 1-8, Jan, 2019.
dc.identifier.doi10.29292/jics.v14i2.34
dc.identifier.issn1872-0234
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3744
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rightsAcesso Aberto
dc.rights.licenseOpen Journal Systems "Este é um artigo publicado em acesso aberto sob uma licença de código aberto (GPL v2). Fonte: https://www.scopus.com/inward/record.uripartnerID=HzOxMe3b&scp=85076531299&origin=inward. Acesso em: 26 maio 2022.
dc.subject.otherlanguageDEPAMBBRE and PAMDLE effects
dc.subject.otherlanguageHigh-temperature environment
dc.subject.otherlanguageLCE
dc.subject.otherlanguageNew layout styles
dc.subject.otherlanguageOcto layout style
dc.titlePerformance of OCTO layout style on SOI MOSFET switches under high-temperature operation
dc.typeArtigo
fei.scopus.citations7
fei.scopus.eid2-s2.0-85076531299
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85076531299&origin=inward
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