From double to triple gate: Modeling junctionless nanowire transistors
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5
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2015-03-18
Autores
PAZ, B. C.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
FAYNOT, O.
AVILA-HERRERA, F.
CERDEIRA, A.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
FAYNOT, O.
AVILA-HERRERA, F.
CERDEIRA, A.
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EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
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PAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; AVILA-HERRERA, F.; CERDEIRA, A. From double to triple gate: Modeling junctionless nanowire transistors. EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. March, 2015.
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This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation and experimental measurements for long and short channel devices.