Using the octagonal layout style to implement the pass MOSFET to improve the electrical performance of the CL-LDO voltage regulator

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dc.contributor.authorMARTUCCI, R. F.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-01-12T21:57:37Z
dc.date.available2022-01-12T21:57:37Z
dc.date.issued2018-05-17
dc.description.abstract© The Electrochemical Society.This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL-LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL-LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL-LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL-LDO VRs, via MOSIS Educational Program. The die areas of each CL-LDO VRs are the same and equal to 0.00994mm2.
dc.description.firstpage91
dc.description.issuenumber8
dc.description.lastpage96
dc.description.volume85
dc.identifier.citationMARTUCCI, R. F.; GIMENEZ, S. Using the octagonal layout style to implement the pass MOSFET to improve the electrical performance of the CL-LDO voltage regulator. ECS Transactions, v. 85, n.8, p. 91-96, Mayo, 2018.
dc.identifier.doi10.1149/08508.0091ecst
dc.identifier.issn1938-5862
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3806
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleUsing the octagonal layout style to implement the pass MOSFET to improve the electrical performance of the CL-LDO voltage regulator
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-85050082310
fei.scopus.subjectBipolar complementary metal oxide semiconductor
fei.scopus.subjectEducational program
fei.scopus.subjectElectrical performance
fei.scopus.subjectLDO voltage regulators
fei.scopus.subjectManufacturing process
fei.scopus.subjectOpen-loop voltage
fei.scopus.subjectPower supply rejection ratio
fei.scopus.subjectQuiescent currents
fei.scopus.updated2025-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85050082310&origin=inward
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