Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures
Nenhuma Miniatura disponível
Citações na Scopus
4
Tipo de produção
Artigo de evento
Data
2015-10-13
Autores
Rodrido Doria
FLANDRE, D.
TREVISOLLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
TREVISOLLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
Orientador
Periódico
SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices
Título da Revista
ISSN da Revista
Título de Volume
Citação
DORIA, R.; FLANDRE, D.; TREVISOLLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
Texto completo (DOI)
Palavras-chave
Resumo
This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.