Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures
N/D
Tipo de produção
Artigo de evento
Data de publicação
2015-10-13
Texto completo (DOI)
Periódico
SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices
Editor
Texto completo na Scopus
Citações na Scopus
4
Autores
Rodrido Doria
FLANDRE, D.
TREVISOLLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
Orientadores
Resumo
This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
Citação
DORIA, R.; FLANDRE, D.; TREVISOLLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
Palavras-chave
Keywords
Self-Cascode; Silicon-on-Insulator; UTBB
Assuntos Scopus
Analog performance; Back-gate bias; Intrinsic voltage gains; Reverse back bias; Self-cascode; SOI transistors; UTBB; Voltage gain