Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs
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Tipo de produção
Artigo de evento
Data de publicação
2021-08-27
Texto completo (DOI)
Periódico
SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
Editor
Texto completo na Scopus
Citações na Scopus
1
Autores
RODRIGUES, J. C.
MARINELLO, G.
CASSE, M.
BARRAUD, S.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
Orientadores
Resumo
This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.
Citação
RODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices, Aug, 2021.
Palavras-chave
Keywords
Electrical characterization; Low temperature; Multigate transistors; Stacked nanowires; Subthreshold slope; Threshold voltage; Transcondutance
Assuntos Scopus
Electrical characteristic; Electrical characterization; Fin widths; Lows-temperatures; Multigate transistors; Nanowire MOSFETs; Stacked nanowire; Subthreshold slope; Temperature influence; Transcondutance