Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

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dc.contributor.authorRODRIGUES, J. C.
dc.contributor.authorMARINELLO, G.
dc.contributor.authorCASSE, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorVINET, M.
dc.contributor.authorFAYNOT, O.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-04-01T06:03:06Z
dc.date.available2022-04-01T06:03:06Z
dc.date.issued2021-08-27
dc.description.abstractThis paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.
dc.identifier.citationRODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices, Aug, 2021.
dc.identifier.doi10.1109/SBMicro50945.2021.9585748
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4460
dc.relation.ispartofSBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguageElectrical characterization
dc.subject.otherlanguageLow temperature
dc.subject.otherlanguageMultigate transistors
dc.subject.otherlanguageStacked nanowires
dc.subject.otherlanguageSubthreshold slope
dc.subject.otherlanguageThreshold voltage
dc.subject.otherlanguageTranscondutance
dc.titleTemperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-85126134146
fei.scopus.subjectElectrical characteristic
fei.scopus.subjectElectrical characterization
fei.scopus.subjectFin widths
fei.scopus.subjectLows-temperatures
fei.scopus.subjectMultigate transistors
fei.scopus.subjectNanowire MOSFETs
fei.scopus.subjectStacked nanowire
fei.scopus.subjectSubthreshold slope
fei.scopus.subjectTemperature influence
fei.scopus.subjectTranscondutance
fei.scopus.updated2025-01-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85126134146&origin=inward
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