Back bias influence on low-frequency noise of n-type nanowires SOI MOSFETs
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2019-02-11
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MOLTO, A. R.
PAZ. B. C.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
PAZ. B. C.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
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2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
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MOLTO, A. R.; PAZ. B. C.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Back bias influence on low-frequency noise of n-type nanowires SOI MOSFETs. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Feb. 2019.
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© 2018 IEEE.This work presents the influence of back (substrate) bias on the low-frequency noise of fully depleted inversion mode n-FET nanowire transistors with different fin widths. Several gate voltage overdrives were applied (from 0mV to 200mV) with devices working in linear regime. The results showed a noise increase for both positive and negative substrate biases (Vsub) and the changing of γ , from 0.9 with zero back bias down to 0.4 for Vsub = -40V. The results obtained for device with channel length of 1 μ m and fin width of 15nm show a decrease of the spectral noise density with the gate voltage overdrive increase for frequencies below 100Hz, which is characterized by mobility mechanism influence at the power spectrum density noise. It was also possible to see in these devices that the generation and recombination noise with decay of 1/f2 overlaps the 1/f γnoise for frequencies above 100Hz. It was also possible to see the noise increase with Wfin decrease as expected.