Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Proposal of compact analytical modeling for trigate junctionless nanowire transistors

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Tipo de produção

Artigo de evento

Data de publicação

2016-01-29

Texto completo (DOI)

Periódico

2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015

Editor

Citações na Scopus

2

Autores

AVILA HERRERA, F.
CERDEIRA, A.
ESTRADA, M.
PAZ, B. C.
Marcelo Antonio Pavallo

Orientadores

Resumo

A compact analytical model for junctionless nanowire transistors is developed taking into account the fin height and including its capacitance. This model is based on a previous one for double-gate transistors just considering the dependence of the fin height and the short channel effects. The validation has been performed by 3D simulations for structures of 15 nm and 10 nm of height obtaining a very good agreement between modeled and simulated data.

Citação

AVILA HERRERA, F.; CERDEIRA, A.; ESTRADA, M.; PAZ, B. C.; PAVANELLO, M. A. Proposal of compact analytical modeling for trigate junctionless nanowire transistors. 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Jan., 2015.

Palavras-chave

Keywords

fin height capacitance; JLT; Junctionless nanowire transistor model

Assuntos Scopus

3D simulations; Double gate transistor; Fin height; Nanowire transistors; Short-channel effect; Trigate

Coleções

Avaliação

Revisão

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