New method for individual electrical characterization of stacked SOI nanowire MOSFETs
N/D
Tipo de produção
Artigo de evento
Data de publicação
2017-10-18
Texto completo (DOI)
Periódico
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Editor
Texto completo na Scopus
Citações na Scopus
4
Autores
PAZ, B.C.
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
Orientadores
Resumo
A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
Citação
PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, p.1-3, 2018.
Palavras-chave
Keywords
Back gate bias; Mobility; SOI; Stacked nanowires
Assuntos Scopus
Back-gate bias; Electrical characteristic; I-V measurements; Mobility extraction; Nanowire MOSFETs; Temperature dependence; Transport parameters