Avaliação da distorção harmônica de nanofios transistores empilhados
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Tipo de produção
Dissertação
Data
2021
Autores
Carvalho, Cesar Augusto Belchior de
Orientador
Pavanello, M. A.
Periódico
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Citação
CARVALHO, Cesar Augusto Belchior de; PAVANELLO, M. A. Avaliação da distorção harmônica de nanofios transistores empilhados. São Bernardo do Campo, 2021. 102 f. Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário FEI, São Bernardo do Campo, 2021 Disponível em: https://doi.org/10.31414/EE.2021.D.131365.
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Palavras-chave
nanofios empilhados,distorção harmônica,porta circundante
Resumo
Este trabalho estuda as características não lineares dos transistores nanofios empilhados,
implementados em tecnologia SOI (silicon-on-insulator), operando como amplificadores
operacionais de um único transistor. São estudadas as influências da largura do nanofio, do
comprimento de canal e do nível de inversão em que os nanofios são polarizados. A não
linearidade é especialmente relevante para as aplicações analógicas, cujos sinais de saída podem
sofrer distorções em decorrência do desempenho do componente, comprometendo a
transmissão e/ou amplificação dos sinais. Após realizar uma análise evolutiva das tecnologias,
o trabalho demonstra que a arquitetura do dispositivo estudado está composta em dois níveis,
sendo um transistor de porta tripla (trigate) e um transistor de porta circundante (gate-allaround).
A revisão bibliográfica aborda alguns dos parâmetros elétricos de maior importância
no estudo dos transistores, conceituando-os fisicamente e expondo suas equações
características. A primeira etapa do trabalho ainda apresenta algumas das propriedades
analógicas investigadas previamente, tais como a tensão de limiar, corrente de dreno, efeito de
corpo, inclinação de sublimiar e a transcondutância, indicando a superioridade dos nanofios
empilhados em relação ao SOI de porta única em alguns aspectos, sobretudo na capacidade de
fornecimento de corrente de dreno, o que está alinhado com o aumento da possibilidade de
integração da tecnologia tão almejada pelo setor mercadológico. O trabalho se dedica a
apresentar a distorção harmônica e seus efeitos em circuitos e sistemas elétricos, indicando que
o fenômeno possui grande importância em áreas diversas, sendo influente tanto em um único
amplificador como em instalações elétricas e equipamentos indústriais mais complexos. Para
obter este parâmetro no objeto de interesse, foi utilizado o método da função integral (IFM),
que permite adquirir os dados apenas com a curva da corrente de dreno em função da tensão de
porta (IDS x VGS) extraída experimentalmente, eliminando-se a necessidade de medições de
corrente alternada (AC), que podem trazer ruídos mais difíceis de serem dissociados do sinal
real dada a magnitude da corrente do dispositivo nanométrico. Os resultados demonstram que
a distorção harmônica dos nanofios empilhados é majoritariamente relacionada ao harmônico
de segunda ordem (HD2), cujo valor se distancia em 30 dB do terceiro harmônico. Os dados
apresentados indicam que os nanofios com maiores WFIN possuem maior não linearidade e
menor ganho de tensão em malha aberta: em relação ao conjunto de transistores com
comprimento fixo L = 100 nm, a maior distorção harmônica se deu para o componente com
largura WFIN = 40 nm, que apresentou distorção harmônica total THD ˜ -19 dB e ganho em
malha aberta Av ˜ 38 dB para maiores valores de gm/IDS, operando em inversão moderada. Já
para os transistores nanofios com largura fixa de WFIN = 10 nm, foi possível observar que a
maior não linearidade ocorre em transistores com maiores comprimentos: para os nanofios
empilhados de L = 400 nm, obteve-se THD ˜ -19 dB em maiores valores de gm/IDS. A relação
obtida entre as dimensões físicas dos transistores e a distorção harmônica são justificadas
através das equações matemáticas apresentadas, sendo que a correlação entre os maiores
resultados de THD para os nanofios com maiores WFIN também é explicada a partir da maior
variação de dgm/dVGT, em acordo com resultados da literatura observados para nanofios com
um único nível. Ao fim do trabalho, novas análises são realizadas para um novo conjunto de
dados, formados por nanofios com múltiplos fins. As maiores magnitudes de corrente de dreno
permitiram evidenciar os resultados e confirmar, com maior grau de confiabilidade, a relação
entre as não-linearidades e as características dimensionais dos nanofios, uma vez que os dados
trazem uma média de resultados de diversos dispositivos operando em paralelo.
This work studies the nonlinear characteristics of stacked nanowire transistors, implemented in SOI (silicon-on-insulator) technology, operating as operational amplifiers of a single transistor. The influence of the nanowire width, channel length and inversion level at which the nanowires are biased are studied. The effect is especially relevant for analog applications, whose output signals may suffer distortions due to the component's performance, compromising the transmission and/or amplification of the signals. After conducting an analysis of the technology’s evolution, the research shows that the studied device's architecture is composed of two levels, being a trigate transistor and a GAA (gate-all-around). The literature review addresses some of the most important electrical parameters in the study of transistors, conceptualizing them physically and exposing their characteristic equations. The first stage of the work still presents some of the analog properties previously investigated, such as threshold voltage, drain current, body effect, sub-threshold slope and transconductance, indicating the superiority of the stacked nanowires in relation to the single-gate SOI in some aspects, especially in the capacity to supply drain current, which tends to increase the technology integration, desired by the market. The work is dedicated to presenting harmonic distortion and its effects on electrical circuits and systems, indicating that the phenomenon has great importance in several areas, being influential both in a single amplifier and in more complex electrical installations and industrial equipment. In order to obtain this parameter in the object of interest, the integral function method (IFM) was used, which allows data to be acquired only with drain current versus gate voltage curve (IDS x VGS), eliminating the need for alternate current (AC) measurements, which can bring more difficult noise to be dissociated from the actual signal given the magnitude of the current of the nanometric device. The results demonstrate that the harmonic distortion of the stacked nanowires is mainly related to the second order harmonic (HD2), whose value is 30 dB above from the third harmonic. The presented data indicate that the nanowires with higher WFIN had major non-linearity and lower open loop voltage gain: in relation to the set of transistors with fixed length L = 100 nm, the greatest harmonic distortion occurred for the component with WFIN = 40 nm, which presented total harmonic distortion THD ˜ -19 dB and open loop voltage gain Av ˜ 38 dB for higher gm/IDS values, operating in moderate inversion. For the nanowire transistors with fixed width of WFIN = 10 nm, it was possible to observe that the major non-linearity occurs in transistors with greater lengths: for stacked nanowires of L = 400 nm, THD ˜ -19 dB was obtained on higher gm/IDS values. The relation obtained between the physical dimensions of the nanowires transistors and the harmonic distortion are justified through the presented equations, being the correlation between the highest THD results for nanowires with higher WFIN also explained by the greater variation of dgm/dVGT, in accordance with literature results observed for single-level nanowires. At the end of the work, new analyzes are carried out for a new set of data formed by nanowires with multiple fins. The higher magnitudes of drain current allowed to evidence the results and confirm, with more reliability, the relationship between non-linearities and the dimensional characteristics of the nanowires, since the data represents an average of results from several devices operating in parallel.
This work studies the nonlinear characteristics of stacked nanowire transistors, implemented in SOI (silicon-on-insulator) technology, operating as operational amplifiers of a single transistor. The influence of the nanowire width, channel length and inversion level at which the nanowires are biased are studied. The effect is especially relevant for analog applications, whose output signals may suffer distortions due to the component's performance, compromising the transmission and/or amplification of the signals. After conducting an analysis of the technology’s evolution, the research shows that the studied device's architecture is composed of two levels, being a trigate transistor and a GAA (gate-all-around). The literature review addresses some of the most important electrical parameters in the study of transistors, conceptualizing them physically and exposing their characteristic equations. The first stage of the work still presents some of the analog properties previously investigated, such as threshold voltage, drain current, body effect, sub-threshold slope and transconductance, indicating the superiority of the stacked nanowires in relation to the single-gate SOI in some aspects, especially in the capacity to supply drain current, which tends to increase the technology integration, desired by the market. The work is dedicated to presenting harmonic distortion and its effects on electrical circuits and systems, indicating that the phenomenon has great importance in several areas, being influential both in a single amplifier and in more complex electrical installations and industrial equipment. In order to obtain this parameter in the object of interest, the integral function method (IFM) was used, which allows data to be acquired only with drain current versus gate voltage curve (IDS x VGS), eliminating the need for alternate current (AC) measurements, which can bring more difficult noise to be dissociated from the actual signal given the magnitude of the current of the nanometric device. The results demonstrate that the harmonic distortion of the stacked nanowires is mainly related to the second order harmonic (HD2), whose value is 30 dB above from the third harmonic. The presented data indicate that the nanowires with higher WFIN had major non-linearity and lower open loop voltage gain: in relation to the set of transistors with fixed length L = 100 nm, the greatest harmonic distortion occurred for the component with WFIN = 40 nm, which presented total harmonic distortion THD ˜ -19 dB and open loop voltage gain Av ˜ 38 dB for higher gm/IDS values, operating in moderate inversion. For the nanowire transistors with fixed width of WFIN = 10 nm, it was possible to observe that the major non-linearity occurs in transistors with greater lengths: for stacked nanowires of L = 400 nm, THD ˜ -19 dB was obtained on higher gm/IDS values. The relation obtained between the physical dimensions of the nanowires transistors and the harmonic distortion are justified through the presented equations, being the correlation between the highest THD results for nanowires with higher WFIN also explained by the greater variation of dgm/dVGT, in accordance with literature results observed for single-level nanowires. At the end of the work, new analyzes are carried out for a new set of data formed by nanowires with multiple fins. The higher magnitudes of drain current allowed to evidence the results and confirm, with more reliability, the relationship between non-linearities and the dimensional characteristics of the nanowires, since the data represents an average of results from several devices operating in parallel.