Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs

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dc.contributor.authorBÜHLER, Rudolf Theoderich
dc.contributor.authorAGOPIAN, P. G. D.
dc.contributor.authorRenato Giacomini
dc.contributor.authorSIMOEN, E.
dc.contributor.authorCLAEYS, C.
dc.contributor.authorMARTINO, J. A.
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-7934-9605
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1060-2649
dc.date.accessioned2022-01-12T22:03:01Z
dc.date.available2022-01-12T22:03:01Z
dc.date.issued2011-10-06
dc.description.abstractThe stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device. © 2011 IEEE.
dc.identifier.citationBÜHLER, R. T.; AGOPIAN, P. G. D.; GIACOMINI, R. SIMOEN, E.; CLAEYS, C.; MARTINO, J. A. Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs. Proceedings - IEEE International SOI Conference, Oct. 2011.
dc.identifier.doi10.1109/SOI.2011.6081677
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4175
dc.relation.ispartofProceedings - IEEE International SOI Conference
dc.rightsAcesso Restrito
dc.titleUniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs
dc.typeArtigo de evento
fei.scopus.citations2
fei.scopus.eid2-s2.0-83455225486
fei.scopus.subjectAnalog performance
fei.scopus.subjectElectric parameters
fei.scopus.subjectFin dimensions
fei.scopus.subjectFin height
fei.scopus.subjectFin length
fei.scopus.subjectReference devices
fei.scopus.subjectSOI n-MOSFETs
fei.scopus.subjectStress levels
fei.scopus.subjectStress profile
fei.scopus.subjectTriple-gate
fei.scopus.subjectUniaxial stress
fei.scopus.subjectVoltage gain
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=83455225486&origin=inward
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