Simulation of miller OpAmp analog circuit with FinFET transistors

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dc.contributor.authorCONTRERAS, E.
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T22:02:34Z
dc.date.available2022-01-12T22:02:34Z
dc.date.issued2012-03-17
dc.description.abstractIn this paper we present a methodology to use the Symmetric Doped Double-Gate Model implemented in Verilog-A to simulate analog circuits with FinFET Technology. A Miller operational Amplifier was simulated in SPICE simulator and the results were validated comparing them with experimental data published in previous works. © 2012 IEEE.
dc.identifier.citationCONTRERAS, E.; CERDEIRA, A.; PAVANELLO, M. A. Simulation of miller OpAmp analog circuit with FinFET transistors. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March. 2012.
dc.identifier.doi10.1109/ICCDCS.2012.6188898
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4144
dc.relation.ispartof2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
dc.rightsAcesso Restrito
dc.subject.otherlanguageFinFET
dc.subject.otherlanguageMiller OpAmp
dc.subject.otherlanguageSDDGM
dc.subject.otherlanguageVerilog-A
dc.titleSimulation of miller OpAmp analog circuit with FinFET transistors
dc.typeArtigo de evento
fei.scopus.citations5
fei.scopus.eid2-s2.0-84860993035
fei.scopus.subjectDouble-gate
fei.scopus.subjectExperimental data
fei.scopus.subjectFinFET
fei.scopus.subjectMiller OpAmp
fei.scopus.subjectMiller operational amplifiers
fei.scopus.subjectSDDGM
fei.scopus.subjectSPICE simulators
fei.scopus.subjectVerilog-A
fei.scopus.updated2024-08-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84860993035&origin=inward
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