Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias
N/D
Tipo de produção
Artigo de evento
Data de publicação
2015-11-20
Texto completo (DOI)
Periódico
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Editor
Texto completo na Scopus
Citações na Scopus
6
Autores
Rodrido Doria
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
Orientadores
Resumo
This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
Citação
DORIA, R.; TREVISOLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Nov. 2015.
Palavras-chave
Keywords
Active Substrate Bias; Analog Behavior; Self-Cascode Structure; UTBB SOI
Assuntos Scopus
Active substrates; Analog behavior; Analog performance; Back-gate bias; Intrinsic voltage gains; Self-cascode; SOI-MOSFETs; UTBB SOI