Drain current and short channel effects modeling in junctionless nanowire transistors
Arquivos
Tipo de produção
Artigo
Data de publicação
2013-01-05
Periódico
Journal of Integrated Circuits and Systems
Editor
Texto completo na Scopus
Citações na Scopus
8
Autores
TREVISOLI, R. D.
Rodrigo Doria
Michelly De Souza
Marcelo Antonio Pavanello
Orientadores
Resumo
© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.
Citação
TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current and short channel effects modeling in junctionless nanowire transistors. Journal of Integrated Circuits and Systems, v. 8, n. 2, 2013.
Palavras-chave
Keywords
Analytical model; Drain induced barrier lowering; Junctionless nanowire transistors; Subthreshold slope