Drain current and short channel effects modeling in junctionless nanowire transistors
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7
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Artigo
Data
2013
Autores
Trevisoli R.D.
Doria R.T.
de Souza M.
Pavanello M.A.
Doria R.T.
de Souza M.
Pavanello M.A.
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Periódico
Journal of Integrated Circuits and Systems
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© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.