Drain current and short channel effects modeling in junctionless nanowire transistors
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2013-01-05
Autores
TREVISOLI, R. D.
Rodrigo Doria
Michelly De Souza
Marcelo Antonio Pavanello
Rodrigo Doria
Michelly De Souza
Marcelo Antonio Pavanello
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Periódico
Journal of Integrated Circuits and Systems
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TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current and short channel effects modeling in junctionless nanowire transistors. Journal of Integrated Circuits and Systems, v. 8, n. 2, 2013.
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© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.