Drain current and short channel effects modeling in junctionless nanowire transistors

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dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorRodrigo Doria
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2023-08-26T23:49:02Z
dc.date.available2023-08-26T23:49:02Z
dc.date.issued2013-01-05
dc.description.abstract© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.
dc.description.firstpage116
dc.description.issuenumber2
dc.description.lastpage124
dc.description.volume8
dc.identifier.citationTREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current and short channel effects modeling in junctionless nanowire transistors. Journal of Integrated Circuits and Systems, v. 8, n. 2, 2013.
dc.identifier.issn1872-0234
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4949
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rightsAcesso Restrito
dc.rights.licenseCreative Commons "Este é um artigo publicado em acesso aberto sob uma licença" Creative commons (CC BY 4.0). Fonte: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84899958318&origin=inward. Disponível em: 29 fev. 2024.
dc.subject.otherlanguageAnalytical model
dc.subject.otherlanguageDrain induced barrier lowering
dc.subject.otherlanguageJunctionless nanowire transistors
dc.subject.otherlanguageSubthreshold slope
dc.titleDrain current and short channel effects modeling in junctionless nanowire transistors
dc.typeArtigo
fei.scopus.citations7
fei.scopus.eid2-s2.0-84899958318
fei.scopus.updated2024-05-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84899958318&origin=inward
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