Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing
N/D
Tipo de produção
Artigo de evento
Data de publicação
2017-06-29
Texto completo (DOI)
Periódico
Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
Editor
Texto completo na Scopus
Citações na Scopus
1
Autores
ASSALTI, R.
Michelly De Souza
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Orientadores
Resumo
© 2017 IEEE.In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated.
Citação
ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, p. 83-86, jun. 2017.
Palavras-chave
Keywords
analog performance; asymmetric self-cascode; back gate voltage; channel width; silicon nanowire
Assuntos Scopus
Analog performance; Back-gate voltages; Channel widths; Self-cascode; Silicon nanowires