Using the Octagonal Layout Style for MOSFETs to boost the Device Matching in Ionizing Radiation Environments
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Artigo
Data
2020-12-04
Autores
PERUZZI , VINICIUS VONO
CRUZ, WILLIAM
SILVA, GABRIEL AUGUSTO DA
SIMOEN, EDDY
CLAEYS, COR
Salvador Gimenez
CRUZ, WILLIAM
SILVA, GABRIEL AUGUSTO DA
SIMOEN, EDDY
CLAEYS, COR
Salvador Gimenez
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Periódico
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
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Citação
PERUZZI , V. V.; CRUZ, W.; SILVA, G. A.; SIMOEN, E.; CLAEYS, C.; SALVADOR, G. Using the octagonal layout Style for MOSFETs to boost the device matching in Ionizing radiation environments. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 20, n. 4, p. 1-6, 2020.
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Palavras-chave
Octo layout style,hardness-by-design technique,MOSFET matching, analog CMOS ICs,Total ionizing dose,Experimental electrical characterization
Resumo
This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha (α) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird's Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.