Fault-tolerant architecture with full recovery under presence of SEU
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2018 IEEE 19th Latin-American Test Symposium, LATS 2018
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EINSFELDT. A.; GIACOMINI, R. Fault-tolerant architecture with full recovery under presence of SEU. 2018 IEEE 19th Latin-American Test Symposium, LATS 2018, p. 1-4, March 2018.
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© 2018 IEEE.A SEU fault-tolerant finite-state machine architecture is presented. It does use less resources than triple redundancy checking techniques and performs a verification to confirm that each operation has been completed without errors, before allowing to step further. A direct addressing technique is used to reduce the risk to advance to an unknown state due to some upsetting event between states. The complete architecture was implemented in a FPGA, including worst-case fault injection structure, to evaluate the reliability. Results have shown effective fault-tolerant behavior and no data loss.