Modeling the interface trap density influence on junctionless nanowire transistors behavior
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2019-02-11
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TREVISOLI, R.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
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2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
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TREVISOLI, R.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A.; Modeling the interface trap density influence on junctionless nanowire transistors behavior. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Feb. 2019.
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This work proposes a methodology for the modeling of the interface traps influence on the electrical characteristics of Junction less Nanowire Transistors. The interface traps can influence the electrical behavior of junction less in both on-and off-states due to the partial depletion regime operation, in which the surface potential varies with the applied biases. The methodology validation is performed using numerical simulations, where the drain current, the trans conductance, the threshold voltage and the subthreshold slope have been analyzed. The modeling considering different traps energetic distributions has been demonstrated.