TREVISOLI, R. D.Rodrido DoriaMichelly De SouzaMarcelo Antonio Pavanello2022-01-122022-01-122012-03-17TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current model for junctionless nanowire transistorsDrain current model for junctionless nanowire transistors. 2012 8th International Caribbeanhttps://repositorio.fei.edu.br/handle/FEI/4140Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.Acesso RestritoArtigo de evento10.1109/ICCDCS.2012.6188924Drain Current ModelJunctionless Devices