Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements

MARINIELLO, G.Rodrido DoriaTREVISOLI, R. D.Michelly De SouzaMarcelo Antonio Pavanello2022-01-122022-01-122012-09-02MARINIELLO, G.; DORIA, R.; TREVISOLI, R. D.; DE SOUZA, M.; PAVANELLO, M. A. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. ECS Transactions, v. 49, n. 1, p. 231-239, 2012.1938-6737https://repositorio.fei.edu.br/handle/FEI/4160Junctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.Acesso RestritoIntrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurementsArtigo de evento10.1149/04901.0231ecst