D'OLIVEIRA, L. M.KILCHYTSKA, V.PLANES, N.FLANDRE, D.Michelly De Souza2022-01-122022-01-122019-10-17D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; DE SOUZA, M. Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Oct. 2019.https://repositorio.fei.edu.br/handle/FEI/3694© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.Acesso RestritoArtigo de evento10.1109/S3S46989.2019.9320715asymmetric structurecomposite transistorlow-powerself-cascodeSOI MOSFETsubthresholdUTBB