NEMER J. P.Michelly De SouzaMarcelo Antonio PavanelloFLANDRE, D.2022-01-122022-01-122012-03-17NEMER J. P.; DE SOUZA, M.; PAVANELLO, M. A. ; FLANDRE, D. Analog performance of submicron GC SOI MOSFETs. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012, March, 2012.https://repositorio.fei.edu.br/handle/FEI/4137This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length. © 2012 IEEE.Acesso RestritoArtigo de evento10.1109/ICCDCS.2012.6188930analog performanceGC SOI MOSFETssubmicron devices