GALEMBECK, E. H.S.RENAUX, C.FLANDRE, D.FINCO, S.Salvador Gimenez2022-01-122022-01-122017-03-05GALEMBECK, E. H.S.; RENAUX, C.; FLANDRE, D.; FINCO, S.; GIMENEZ, S. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, v. 17, n. 1, p. 221-228, Marc, 2017.1558-2574https://repositorio.fei.edu.br/handle/FEI/3846This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 m fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.Acesso RestritoArtigo10.1109/TDMR.2017.2652729high-temperature environmentLCE effect and PAMDLE effectOCTO layout style