Michelly De SouzaRODRIGUES, J. C.MARINIELLO, G.CASSE, M.BARRAUD, S.VINET, M.FAYNOT, O.Marcelo Antonio Pavanello2022-11-012022-11-012022DE SOUZA, M.; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires. IEEE 15th Workshop on Low Temperature Electronics, WOLTE 2022 - Conference Proceedings, jUN. 2022.https://repositorio.fei.edu.br/handle/FEI/4629© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.Acesso RestritoArtigo de evento10.1109/WOLTE55422.2022.9882780GIDLlow temperatureSOIstacked nanowire transistor