Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

MARINIELLO, G.Rodrido DoriaMichelly De SouzaMarcelo Antonio PavanelloTREVISOLI, R. D. G.2022-01-122022-01-122012-03/17MARINIELLO, G.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. ; TREVISOLI, R. D. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March. 2012.https://repositorio.fei.edu.br/handle/FEI/4139Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.Acesso RestritoAnalysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulationsArtigo de evento10.1109/ICCDCS.2012.6188946Gate CapacitanceJunctionless Devices