AGOPIAN, P. G. D.DOS SANTOS, S. D.NEVES, F. S.MARTINO, J. A.VANDOOREN, A.ROOYACKERS, R.SIMOEN, E.CLAEYS, C.2022-01-122022-01-122013-10-10AGOPIAN, P. G. D.; DOS SANTOS, S. D.; NEVES, F. S.; MARTINO, J. A.;VANDOOREN, A.; ROOYACKERS, R.; SIMOEN, E.; CLAEYS, C. NW-TFET analog performance for different Ge source compositions. 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013, Oct. 2013.https://repositorio.fei.edu.br/handle/FEI/4084The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented. © 2013 IEEE.Acesso RestritoArtigo de evento10.1109/S3S.2013.6716561