Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model

MOREIRA, C. V.TREVISOLI, R.Marcelo Antonio Pavanello2022-01-122022-01-122019-02-27MOREIRA, C. V.; TREVISOLI, R.; PAVANELLO, M. A. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. Latin American Electron Devices Conference, LAEDC 2019, Feb. 2019.https://repositorio.fei.edu.br/handle/FEI/3724This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.Acesso RestritoVerilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact ModelArtigo de evento10.1109/LAED.2019.8714741Junctionless TransistorSPICEVerilog-A