Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence

PAZ, B. C.Marcelo Antonio PavanelloCASSE, M.BARRAUD, S.REIMBOLD, G.VINET, M.FAYNOT, O.2022-01-122022-01-122016-01-27PAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016, p. 170-173, Jan. 2016.https://repositorio.fei.edu.br/handle/FEI/3903This work aims to present the analog performance of silicon n-Type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n-and p-Type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage gain in nanowires and quasi-planar transistors. The mobility dependence on the temperature is found to be the key parameter to describe the behavior of both transconductance and output conductance when decreasing temperature.Acesso RestritoAnalog performance of n-and p-FET SOI nanowires including channel length and temperature influenceArtigo de evento10.1109/ULIS.2016.7440080Analog performanceLow temperatureMobility dependenceNanowires