FERREIRA, F. A. L. P.CERDEIRA, A.FLANDRE, D.Marcelo Antonio Pavanello2022-01-122022-01-122009-05-29FERREIRA, F. A. L. P.; CERDEIRA, A.; FLANDRE, D.; PAVANELLO, M. A. Analytical modeling of double gate graded-channel SOI transistors for analog applications. ECS Transactions, v. 19, n. 4, p. 139-144, May, 2009.1938-5862https://repositorio.fei.edu.br/handle/FEI/4269In this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated. ©The Electrochemical Society.Acesso RestritoArtigo de evento10.1149/1.3117402