CERDEIRA, A.ESTRADA, M.TREVISOLI, R. D.Rodrido DoriaMichelly De SouzaMarcelo Antonio Pavanello2022-01-122022-01-122013-09-06CERDEIRA, A.; ESTRADA, M.; TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Analytical model for potential in double-gate juntionless transistors. Chip in Curitiba 2013 - SBMicro 2013: 28th Symposium on Microelectronics Technology and Devices. Sept. 2013.https://repositorio.fei.edu.br/handle/FEI/4097An analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered. © 2013 IEEE.Acesso RestritoArtigo de evento10.1109/SBMicro.2013.6676165Analytical calculation of potentialsJunctionless transistors