DE SOUZA, M.FLANDRE. D.Marcelo Antonio Pavanello2022-06-012022-06-012013-09-06DE SOUZA, M.; FLANDRE. D.; PAVANELLO, M. A. Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. Chip in Curitiba 2013 - SBMicro 2013: 28th Symposium on Microelectronics Technology and Devices. Sept. 2013.https://repositorio.fei.edu.br/handle/FEI/4513This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L 2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation. © 2013 IEEE.Acesso RestritoArtigo de evento10.1109/SBMicro.2013.6676154Analog ParametersAsymmetric Self-cascodeSOI MOSFET