Pavanello M.A.Martino J.A.Simoen E.Claeys C.2019-08-192019-08-192005PAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor. Analysis of Temperature Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETs. IEEE Transactions on Electron Devices, v. 52, n. 10, p. 2236-2242, 2005.0018-9383https://repositorio.fei.edu.br/handle/FEI/1063This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation. © 2005 IEEE.Acesso RestritoArtigo10.1109/TED.2005.856799Drain-induced barrier lowering (DIBL)Fully depletedLow temperatureMOSFETSilicon-on-insulator (SOI)