CONTRERAS, E.CERDEIRA, A.ALVARADO, J.Marcelo Antonio Pavanello2023-08-262023-08-262010-09-05CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; PAVANELLO, M. A. Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors. Journal of Integrated Circuits and, v. 5, n. 2, p. 110-115, sept. 2010.1872-0234https://repositorio.fei.edu.br/handle/FEI/5006The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.Acesso RestritoArtigo2D ATLAS simulationDouble-gate graded-channel transistorSmartspice simulatorSymmetric doped double-gate model