Pavanello M.A.Martino J.A.Simoen E.Claeys C.2019-08-192019-08-192005PAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor. Impact of halo implantation on 0.13?m floating body partially depleted SOI n-MOSFETs in low temperature operation. Solid-State Electronics, v. 49, n. 8, p. 1274-1281, 2005.0038-1101https://repositorio.fei.edu.br/handle/FEI/1061This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature. © 2005 Elsevier Ltd. All rights reserved.Acesso RestritoArtigo10.1016/j.sse.2005.06.007DIBLLow temperaturePartially depletedSelf-heatingSilicon-on-insulatorThermal resistance