CONTRERAS, E.CERDEIRA, A.ALVARADO J.Marcelo Antonio Pavanello2022-01-122022-01-122009-09-03CONTRERAS, E.; CERDEIRA, A.; ALVARADO J.; PAVANELLO, M. A. Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors. ECS Transactions, v. 23, n. 1, p. 597-604, Sept. 2009.1938-5862https://repositorio.fei.edu.br/handle/FEI/4272The development of models to simulate circuits containing new devices is an important task to allow for the introduction of these devices in practical applications. In this paper we show the advantages of using the Symmetric Doped Double-Gate Model recently developed and are already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. A current-mirror circuit using GC devices has been simulated and the results were validated comparing them with those obtained in MIXED-MODE and two-dimensional ATLAS simulation of the GC devices. © The Electrochemical Society.Acesso RestritoArtigo de evento10.1149/1.3183769