LOESCH, D. S.Salvador GimenezSWART, J. W.Marcilei Aparecida Guazzelli2022-01-122022-01-122018-Aug-3LOESCH, D. S.; GIMENEZ, S.; SWART, J. W.; GUAZZELLI, M. A. Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node. 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018, Aug. 2018.https://repositorio.fei.edu.br/handle/FEI/3764This paper aims to evaluate the impact of the octagonal layout style for MOSFETs regarding the 180nm Bulk CMOS ICs technology node. The main results of this study show that the nMOSFETs with octagonal gate geometries are capable of improving the drain current, Early voltage, intrinsic voltage gain, and on-state drain to source resistance about 150%, 800%, 66% and 50%, respectively, in relation to the standard rectangular MOSFET counterparts, regarding the same bias conditions. Therefore, the LCE and PAMDLE effects continue being actives regarding this 180 nm Bulk CMOS ICs technology node.Acesso RestritoArtigo de evento10.1109/SBMicro.2018.8511476Electrical characterizationLCEOctagonal layout styleOCTO MOSFETPAMDLE