BENFICA, J.GREEN, B.PORCHER, B. C.POEHLS, L. B.VARGAS, F.MEDINA, N. H.ADDED, N.AGUIAR, V. A. P. DEMACCHIONE, E. L. A.AGUIRRE, F.Marcilei Aparecida Guazzelli2022-01-122022-01-122016-05-17BENFICA, J.; GREEN, B.; PORCHER, B. C.; POEHLS, L. B.; VARGAS, F.; MEDINA, N. H.; ADDED, N.;AGUIAR, V. A. P. DE; MACCHIONE, E. L. A.; AGUIRRE, F.; GUAZZELLI, M. A. Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID. 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2016, p. 887-889, mayo, 2016.https://repositorio.fei.edu.br/handle/FEI/3894© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.Acesso RestritoArtigo de evento10.1109/APEMC.2016.7522900Combined TestEMIPower-Supply NoiseSEU SensitivitySpartan 3ESRAM-Based FPGATID