CLAEYS, C.PUT, S.RAFI, J. M.Marcelo Antonio PavanelloMARTINO, J. A.SIMOEN, E.2022-01-122022-01-122009-06-02CLAEYS, C.; PUT, S.; RAFI, J. M.; PAVANELLO, M. A.; MARTINO, J. A.; SIMOEN, E. Reliability performance characterization of SOI FinFets. 2009 2nd International Workshop on Electron Devices and Semiconductor Technology, IEDST '09. Jun. 2022.https://repositorio.fei.edu.br/handle/FEI/4263FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages. ©2009 IEEE.Acesso RestritoArtigo de evento10.1109/EDST.2009.5166090Drain current transientsFinFetsLow-frequency noiseMuGFETsSOI