Marcelo Antonio PavanelloMARTINO, J. A.CHUNG, T. M.KRANTI, A.RASKIN, J. P.FLANDRE, D.2023-08-262023-08-262003-10-16PAVANELLO, M. A.; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D. Operation of double gate graded-channel transistors at low temperatures. Proceedings - Electrochemical Society, v. 27, p. 50-60, oct. 2003.https://repositorio.fei.edu.br/handle/FEI/5070This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.Acesso RestritoArtigo de evento