CERDEIRA, A.ALEMAN, M. A.Marcelo Antonio PavanelloMARTINO, J. A.VANCAILLIE, L.FLANDRE, D.2023-08-262023-08-262004-11-05CERDEIRA, A.; ALEMAN, M. A.; PAVANELLO, M. A.; MARTINO, J. A.; VANCAILLIE, L.; FLANDRE, D. On-resistance and harmonic distortion in graded-channel SOI FD MOSFET. Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS, p. 118-121, nov. 2004.1541-6275https://repositorio.fei.edu.br/handle/FEI/5059In this paper we analyze the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications, i.e. on-resistance and non-linear harmonic distortion, is supported by measurements on conventional and Graded-Channel (GC) fully depleted (FD) SOI MOSFETs. The quasi linear I-V characteristics of GC transistors demonstrate a decrease of the on-resistance as the length of the low doped region into the channel is augmented and an improvement of the third order harmonic distortion (HD3), when compared with conventional transistors. A full comparison method between conventional and GC SOI MOSFETs is presented considering HD3 evolution with on-resistance tuning under low voltage of operation, demonstrating the significant advantages of the asymmetrical long channel transistors. © 2004 IEEE.Acesso RestritoArtigo de evento